1. Field of the invention
The present invention relates to an address buffer circuit of a semiconductor memory device, and more particularly, to an address buffer circuit capable of selectively inputting a plurality of address signals.
2. Description of the related art
High integration and high-speed operation are required in semiconductor memory devices. However, high integration has required operating voltages within semiconductor memory devices. This, in turn, has caused reaction speed with respect to input signals to decrease, and accordingly, render it difficult to achieve the high-speed operation in the semiconductor memory device.
Furthermore, in semiconductor memory devices, each different address can be used for a plurality of modes. For example, a dynamic random access device contains a normal mode (read mode & write mode) and a CBR mode (CAS Before RAS mode, wherein, CAS: Column Address Strobe and RAS: Row Address Strobe), and inputs different kinds of addresses according to the characteristics of each mode to thereby select memory cells corresponding to the input addresses.
The normal mode includes a read and write mode for selecting memory cells corresponding to addresses input from outside of the semiconductor memory device. In this normal mode, a CAS signal is enabled after a RAS signal is enabled. The CBR mode executes a refresh mode. In the refresh mode, refresh address signals generated from an internal counter are input and memory cells corresponding to the input refresh addresses are selected. The generation speed of refresh address signals is slower than that of normal read and write address signals. Since the same address buffer circuit is commonly used for both normal and refresh modes, the slower refresh address signals disturb the speed of address buffer circuit.
FIG. 1 shows the address buffer circuit of one conventional dynamic random access memory device, and hereinafter operations in the normal mode and the refresh mode will be explained.
A resistor 22 is connected to a power supply voltage V.sub.CC. A PMOS transistor 11 is connected between the resistor 22 and a node N11, and has its gate electrode connected to an external address signal AI. A NMOS transistor 12 is connected between the node N11 and a node N12, and has its gate electrode connected to a row address enable signal PRAE. An NMOS transistor 13 is connected between the node N12 and a node N13, and has its gate electrode connected to the external address signal AI. An NMOS transistor 14 is connected between the node N13 and a ground potential V.sub.SS, and has its gate electrode connected to a row address strobe signal PRASB. A PMOS transistor 15 is connected between the power supply voltage V.sub.CC and the node N11, and has its gate electrode connected to the row address enable signal PRAE. A PMOS transistor 16 is connected between the power supply voltage V.sub.CC and the node N11, and has its gate electrode connected to the row address strobe signal PRASB. An inverter 21 inverts the row address strobe signal PRASB. A PMOS transistor 17 is connected between the power supply voltage V.sub.CC and a node N14, and has its gate electrode connected to an output terminal of the inverter 21. A PMOS transistor 18 is connected between the node N14 and a node N1, and has its gate electrode connected to the node N11. An NMOS transistor 19 is connected between the node N1 and a node N15, and has its gate electrode connected to the node N11. An NMOS transistor 20 is connected between the node N15 and the ground voltage V.sub.SS, and connected to the row address strobe signal PRASB at a gate electrode thereof. The construction as described above is used as a first input of the external address signal AI in the normal mode.
Operation of the first input will now be explained. An input margin of the external address signal AI is designated by the row address enable signal PRAE and the row address strobe signal PRASB which are used as external address input control signals.
In an initial state, the row address enable signal PRAE is in a logic "low" state and the row address strobe signal PRASB is in a logic "high" state. In this case, the NMOS transistor 12 is turned off and the PMOS transistor 15 is turned on, and therefore, the node N11 is charged to a level of the power supply voltage V.sub.CC. Accordingly, since the NMOS transistor 12 is in the turned-off state, the external address signal AI is not input. Further, since the row address strobe signal PRASB with a logic "high" state is input, the PMOS transistor 16 is turned off and the NMOS transistor 20 is turned on. Because the PMOS transistor 17, which is connected to the inverter 21 at the gate electrode thereof, is in the turned-on state, the potential of the power supply voltage V.sub.CC is generated at the node N1.
If the row address enable signal PRAE is then changed to a logic "high" state, the NMOS transistor 12 is turned on and the PMOS transistor 15 is turned off. Accordingly, an input path of the external address signal AI is formed. If the external address signal AI is input as a logic "high" state, the PMOS transistor 11 is turned off and the NMOS transistor 13 is turned on. Therefore, a logic "low" potential is generated at the node N11. Then, the PMOS transistor 18 and the NMOS transistor 19, which have their gate electrodes connected in common to the node N11, are respectively turned on and off, and the power supply voltage potential V.sub.CC is generated at the node N1.
Alternatively, if the external address signal AI is input at a logic "low" level, the PMOS transistor 11 is turned on and the NMOS transistor 13 is turned off. Therefore, the power supply voltage potential V.sub.CC will be generated at the node N11. The PMOS transistor 18 and the NMOS transistor 19, which have their gate electrodes connected to the node N11 are thereby respectively turned off and on, to generate a logic "low" potential (ground potential) at the node N1.
Thus, if the row address enable signal PRAE is changed to the logic "high" state, the first input is enabled, thereby outputting a logic signal corresponding to the node N1 according to the logic of the input external address signal AI. However, if the row address strobe signal PRASB is changed to the logic "low" state, the NMOS transistor 14 is turned off and the PMOS transistor 16 is turned on, causing the input path of the external address signal AI to be cut off and causing the node N11 to be charged to the power supply voltage V.sub.CC level. Additionally, the NMOS transistor 20 is turned off and the PMOS transistor 17 is also turned off by the inverter 21, thereby disconnecting the paths of the first input and the node N1.
Therefore input of the external address signal AI is enabled from the time when the row address enable signal PRAE is changed to the logic "high" state to the time when the row address strobe signal PRASB is changed to the logic "low" state. During this period, the external address signal AI is input.
A second input for inputting the counter output CNT will now be described. An inverter 31 inverts a row count PRCNT to thereby output the inverted result to a node N21. A transmission gate 32 includes NMOS and PMOS transistors which are connected between an input terminal of a counter output CNT and a node N22. In transmission gate 32, a gate electrode of the NMOS transistor is connected to the node N21 and a gate electrode of the PMOS transistor is connected to the row count PRCNT. Accordingly, the transmission gate 32 is turned on when the row count PRCNT maintains the logic "low" state, and will transmit the counter output CNT to the node N22.
An inverter 33 is connected between the nodes N22 and N23, and an inverter 34 is connected between the nodes N23 and N22. The inverters 33 and 34 are used as a latch for the signal from node N22. A transmission gate 35 includes NMOS and PMOS transistors which are connected between the nodes N23 and N1. In this transmission gate 35, a gate electrode of the PMOS transistor is connected to the node N21 and a gate electrode of the NMOS transistor is connected to the row count PRCNT. Accordingly, the transmission gate 35 is turned on when the row count PRCNT maintains the logic "high" state, and transmits the counter output CNT being latched at the node N23 to the node N1.
In this second input, if the row count PRCNT is input as a logic "low" state, the transmission gate 32 is turned on and the transmission gate 35 is turned off. Accordingly, if the row count PRCNT is a logic "low", the transmission gate 32 transmits the input counter output CNT to the node N22, and the inverters 33 and 34 latch the counter output CNT which is transmitted to the node N22 to the node N23. Since the transmission gate 35 is in the turned-off state, the counter output CNT latched to the node N23 is cut off and not transmitted to the node N1.
However, the row count PRCNT is then changed to a logic "high" state, the transmission gate 32 is turned off and the transmission gate 35 is turned on. Accordingly, if the row count PRCNT is in the logic "high" state, the transmission gate 32 prevents the counter output CNT from being input, and the transmission gate 35 transmits the counter output CNT latched to the node N23 to the node N1.
Construction of an address input will now be described. An inverter 51 is connected between the node N1 and a node N31, and an inverter 52 is connected between the nodes N31 and N1. The inverters 51 and 52, which are used as a latch, latch an address signal of the node N1 to the node N31. A NAND gate 54 inputs an address signal of the node N31 and an address enable signal PRAR to thereby NAND the input signals. The inverter 53 inverts the address signal of the node 31 to thereby output the inverted address signal. A NAND gate 55 inputs an output of the inverter 53 and the address enable signal PRAR to thereby NAND the input signals. An inverter 56 inverts an output of the NAND gate 54 to thereby output the inverted result as a second row address input RAIB. An inverter 57 inverts an output of the inverter 55 to thereby output the inverted output as a first row address signal input RAI.
Operation of the address output will now be described. The external address signal AI or counter output CNT input to the node N1 is latched to the node N31 by the inverters 51 and 52. At this time, an output of the latched address signal of the node N31 is controlled by the address enable signal PRAR. That is, if the address enable signal PRAR is input as the logic "low" state, the NAND gates 54 and 55 output the signals of the logic "high" states regardless of the address signal of the node N31. Thus, if the address enable signal PRAR is not in a logic "high" state, the address signal of the node N31 is not output.
However, if the address enable signal PRAR is changed to the logic "high" state, the NAND gates 54 and 55 output NANDed signals, the logic states of which depend on the logic states of the address signal of the node 31 and the addresses signal inverted by the inverter 53.
If the address signal of the node N1 is the logic "high" state, the inverter 51 inverts the address signal of the node N1 to thereby output the signal of the logic "low" state to the node N31, and the NAND gate 54 NANDs the address signal with the node N31 and the address enable signal PRAR of the logic "high" state to thereby output the NANDed signal with a logic "high" state. The inverter 56 inverts the output of the NAND gate 56 to thereby yield the inverted result as the second row address input RAIB with a logic "low" state. Also, in a similar manner, the first row address input RAI output from the inverter 57 becomes the logic "high" state. Accordingly, the first row address input RAI and the second row address input RAIB have complementary logic states to each other.
In the conventional address buffer constructed as described above, all the address signals input therein are output during the same period. That is, the output of the address signal is determined according to a period of the address enable signal PRAR. Accordingly, first and second output address signals are enabled during the time when the address enable signal PRAR is maintained in the logic "high" state. As a result, the external address signal AI and the counter output CNT are output during the same period.
Generally, a dynamic random access memory is intended to operate at a high-speed by reducing a margin (time period) of the external address signal AI input in the normal mode, and performs the refresh operation of the memory cell by relatively increasing a margin of the counter output mode has to be longer than that of the normal mode. However, in the address buffer circuit as discussed above, the margins of the normal mode and the refresh mode have to be identically designated. In this case, the period of the address enable signal PRAR has to be designated as the margin of the refresh mode executed at a slow speed and therefore, the margin of the external address in the normal mode can not be relatively reduced. Thus, a limit is placed on high speed memory access in conventional devices.
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